1. Field of the Invention
The present invention relates to memory devices, and more particularly to a memory device having a plurality of memory cells for storing multi-valued (e.g. binary) information.
2. Description of the Background Art
Memory devices having a plurality of memory cells for storing, e.g., binary information include SRAM (Static Random Access Memory).
FIG. 4 shows an example of structure of an SRAM memory array. As shown in FIG. 4, this SRAM memory array includes a plurality of memory cells MC successively arranged in a line. A write bit line WBL, an inverted data write bit line /WBL, and a read bit line RBL are connected to each memory cell MC. In this specification, the symbol xe2x80x9c/xe2x80x9d denotes logically inverted signal (the same applies hereinafter).
Each memory cell MC is disposed between the write bit line WBL and the inverted data write bit line /WBL and read bit line RBL. As well as these bit lines, read word lines and write word lines are also connected to the memory cells MC (neither is shown in FIG. 4).
In the SRAM memory array shown in FIG. 4, the bit lines for carrying write data or read data and the word lines for selecting memory cells are provided for writing and for reading, respectively. Thus this SRAM memory array is of multiport type which allows write and read operations to be simultaneously performed in the same clock cycle.
Input data DI is provided to the write bit line WBL and the inverted data write bit line /WBL through a write driver 1 for driving both write bit lines. More specifically, the input data DI is given to the write bit line WBL through an inverter I1 in the write driver 1. Also, the input data DI is given to the inverted data write bit line /WBL through a series connection of inverters I2 and I3 in the write driver 1.
On the other hand, output data DO is outputted from the read bit line RBL through an inverter I4 as a read driver for driving data output line.
FIG. 5 shows an example of the structure of the SRAM circuit in the memory cell MC shown in FIG. 4. As shown in FIG. 5, this memory cell MC includes a latch circuit formed of inverters MI1 and MI2 each having its input connected to the other""s output, an N-channel MOS transistor MN1 having its source connected to the output of the inverter MI2, and an N-channel MOS transistor MN2 having its source connected to the output of the inverter MI1.
The write bit line WBL is connected to the drain of the N-channel MOS transistor MN1 and the inverted data write bit line /WBL is connected to the drain of the N-channel MOS transistor MN2. The write word line WWL is connected to the gates of the N-channel MOS transistors MN1 and MN2 in common.
The memory cell MC also includes an inverter MI3 connected to the source of the N-channel MOS transistor MN1, for reading data from the latch circuit. The output of the inverter MI3 is connected to the source of an N-channel MOS transistor MN3. The read bit line RBL is connected to the drain of the N-channel MOS transistor MN3 and the read word line RWL is connected to its gate.
The memory cell MC is thus formed with a plurality of inverters and transistors.
Now, in the SRAM memory array shown in FIG. 4, the N-channel MOS transistor MN1 in each memory cell MC is connected to the write bit line WBL, the N-channel MOS transistor MN2 in each memory cell MC is connected to the inverted data write bit line /WBL, and the N-channel MOS transistor MN3 in each memory cell MC is connected to the read bit line RBL.
In general, parasitic capacitance is present in MOS transistors. Accordingly, when driving at least one of the write bit line WBL, inverted data write bit line /WBL and read bit line RBL that are respectively connected to the drains of the N-channel MOS transistors MN1 to MN3, the bit line is loaded with the drain-substrate capacitances of the MOS transistors in the individual memory cells MC.
Therefore, in order to reduce the load capacitance, all memory cells in the memory device are divided into a plurality of local blocks. In other words, some memory cells are grouped into a block and a plurality of blocks are combined to form a memory device. FIG. 6 is a diagram showing an example of the structure of an SRAM memory array divided into blocks.
As shown in FIG. 6, local blocks LB0 to LBm (m is a positive number), each including some memory cells MC, are successively arranged in a line. A global write bit line GWBL and a global read bit line GRBL are connected to the local blocks LB0 to LBm in common. The local blocks LB0 to LBm are disposed between the global write bit line GWBL and the global read bit line GRBL.
The global write bit line GWBL receives input data DI and the global read bit line GRBL outputs output data DO through an inverter I4 as a read driver for driving data output line.
In each of the local blocks LB0 to LBm, a plurality of memory cells MC are successively arranged in a line. In the mth block, a local write bit line LWBLm, a local inverted data write bit line /LWBLm, and a local read bit line LRBLm are connected to each memory cell MC.
In the mth block, the memory cells MC are disposed between the local write bit line LWBLm, and the local inverted data write bit line /LWBLm and local read bit line LRBLm. In addition to these lines, local read word lines and local write word lines (neither is shown in FIG. 6) are also connected to the memory cells MC.
In the mth block, the local write bit line LWBLm and the local inverted data write bit line /LWBLm are supplied with the input data DI from the global write bit line GWBL through a local write driver 1m for driving both write bit lines. More specifically, the input data DI is given to the local write bit line LWBLm through an inverter I1m in the local write driver 1m. Also, the input data DI is given to the local inverted data write bit line /LWBLm through a series connection of inverters I2m and I3m in the local write driver 1m. 
A write selector SWm is provided between the global write bit line GWBL and the write driver 1m. The write selector SWm is a switch circuit for providing the input data DI applied to the global write bit line GWBL to a proper block. For example, the write selector SWm is formed as an AND circuit whose one input end is connected to the global write bit line GWBL and whose other input end receives a write block select signal BWm.
On the other hand, the local read bit line LRBLm is connected to the global read bit line GRBL through a read selector SRm. The read selector SRm, too, is a switch circuit, which gives stored data from a proper block to the global read bit line GRBL. For example, the read selector SRm, too, is formed as an AND circuit whose one input end is connected to the local read bit line LRBLm and whose other input end receives a read block select signal BRm.
While the structure of the mth block has been described above, the 0th and other blocks are constructed in the same way.
When the memory cells are divided into blocks as shown above, the drain-substrate capacitances of MOS transistors in the memory cells MC are applied as load only to the local write bit line LWBLm, the local inverted data write bit line /LWBLm, and the local read bit line LRBLm provided in the block to which those memory cells MC belong. Accordingly, when the memory arrays in FIGS. 4 and 6 have the same number of memory cells MC in total and the individual blocks in FIG. 6 include the same number of memory cells MC, the local write bit line LWBLm, the local inverted data write bit line /LWBLm, and the local read bit line LRBLm in FIG. 6 are subjected to a load capacitance that is 1/(m+1) of the load capacitance to the write bit line WBL, the inverted data write bit line/WBL, and the read bit line RBL in FIG. 4.
Reducing the load capacitance to each bit line suppresses interconnection delay, and therefore dividing the memory cells into blocks as shown above speeds up write and read operations to and from the memory cells MC.
While FIG. 6 does not show local read word lines and local write word lines to the memory cells MC in the individual blocks, one memory cell MC in the memory device may be selected as shown below in writing or reading of information.
Specifically, the memory cells MC are grouped so that the individual local blocks LB0 to LBm include the same number of memory cells MC and an in-block memory cell select signal is generated to select one memory cell MC in each block in a common manner among the individual local blocks. A local block is selected by using the write block select signal BWm or the read block select signal BRm. For example, such a technique is described in Japanese Patent Application Laid-Open No. 8-96579 (1996): the signal shown as numerical number 14 in FIG. 1 in the specification corresponds to the in-block memory cell select signal and the signal shown as numerical number 15 corresponds to the read block select signal BRm.
However, when one memory cell MC is selected in common in each local block, one memory cell MC is activated in each local block, which consumes wasteful power. That is, in FIG. 6, for example, when the read word line RWL in one memory cell MC is activated in each of the local blocks LB0 to LBm, currents flow from the inverters MI3 in those memory cells MC to the individual local read bit lines LRBL0 to LRBLm in the individual local blocks LB0 to LBm. This means that current flows to the local read bit lines in unselected local blocks, consuming wasteful power.
Also, when the memory cells are divided into blocks as shown in FIG. 6, each block requires circuits as interfaces between the local and global write bit lines and between the local and global read bit lines (in FIG. 6, the local write driver 1m, the write selector SWm, and the read selector SRm). Providing such an increased number of interface circuits increases the chip area, which hinders size reduction and cost reduction of the memory device.
Write and read operations of the memory device can be speeded up by reducing the number of memory cells included in each block, but reducing the number of memory cells in each block while maintaining the storage capacity inevitably requires increasing the number of blocks. Increasing the number of blocks means increasing the number of interface circuits. Thus the speeding up of the memory device has been in a trade-off relation with the size reduction and cost reduction.
An object of the present invention is to provide a memory device that consumes no wasteful power when selecting memory cells, and also a memory device that achieves high operating speed and size and cost reductions.
According to a first aspect of the present invention, a memory device includes a plurality of memory cells for storing information. The plurality of memory cells are divided into a plurality of local blocks. The plurality of local blocks each contain the same number of memory cells.
In the memory device, in writing of the information to one of the memory cells, or in reading of the information from one of the memory cells, one of the plurality of local blocks is specified, and one of the same number of memory cells is specified in each local block in a common manner, and thereby only one memory cell in one local block is activated.
In writing or reading, one of the plurality of local blocks is specified, and one of the same number of memory cells is specified in each local block in a common manner, and thereby only a single memory cell in a single local block is activated. Thus unselected other memory cells are not activated, thereby providing a memory device that consumes no wasteful power when selecting memory cells.
According to a second aspect of the present invention, a memory device has a plurality of memory cells for storing information. The plurality of memory cells are divided into a plurality of local blocks. The plurality of local blocks are arranged in a plurality of lines in a first direction and are arranged in a plurality of lines in a second direction that is different from the first direction.
The memory device further includes a plurality of local read bit lines, a global read bit line, and a write bit line.
The local read bit line is provided in each of the plurality of local blocks and connected in common to all memory cells within that local block.
The global read bit line extends along the first direction, and is selectively connected to one of a plurality of the local read bit lines through a branch line extending along the second direction in read operation.
The write bit line extends along the first direction and connected to all of the plurality of memory cells through branch lines extending along the second direction.
The plurality of local blocks are arranged in the first and second directions, a plurality in each direction. Therefore both bit lines can be shorter than in an arrangement in which all local blocks are arranged in a line in the first direction and the global read bit line and the write bit line are extended in the first direction. This achieves higher speed signal transmission on both bit lines. Furthermore, according to the invention, the read bit lines include local and global lines and the write bit line is connected to all memory cells in common. It is necessary to drive the read bit line in the individual memory cells, and the load capacitance to the bit line can be reduced by adopting the local read bit lines, which increases the signal transmission speed. On the other hand, the write bit line is driven with a buffer having a large driving capability to withstand the load capacitance of all memory cells connected in common. This eliminates the need to provide a local write bit line and a driving buffer in each local block, thus preventing an increase in circuit scale. Moreover, according to the invention, a plurality of local blocks are arranged not only in the first direction but also in the second direction and the global read bit line and the write bit line are respectively connected to the local read bit lines and the memory cells through branch lines extending along the second direction. Accordingly, as compared with an arrangement in which memory devices are simply arranged in a plurality of lines, with each memory device having a plurality of local blocks all arranged in a line along the first direction and the global read bit line and write bit line extending along the first direction, the bit lines can be shared to reduce the number of interconnections. This reduces interconnection capacitance between bit lines and speeds up signal transmission.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.